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MAX791 microprocessor supervisory circuit ________________________________________________________________ maxim integrated products 1 19-0075; rev. 6; 12/99 general description the MAX791 microprocessor (?) supervisory circuit reduces the complexity and number of components need- ed to monitor power-supply and battery-control functions in ? systems. the 50? supply current makes the MAX791 ideal for use in portable equipment, while the 6ns chip-enable propagation delay and 250ma output capa- bility (25ma in battery-backup mode) make it suitable for larger, higher-performance equipment. the MAX791 comes in 16-pin dip, tssop, and narrow so packages and provides the following functions: p reset. r e s e t output is asserted during power-up, power-down, and brownout conditions, and is guaran- teed to be in the correct state for v cc down to 1v, even with no battery in the circuit. manual-reset input. a 1.25v threshold detector provides for power-fail warning and low-battery detection, or monitors a power supply other than +5v. two-stage power-fail warning. a separate low-line comparator compares v cc to a threshold 150mv above the reset threshold. backup-battery switchover for cmos ram, real-time clocks, ?s, or other low-power logic. software monitoring of backup-battery voltage. a watchdog-fault output is asserted if the watchdog input has not been toggled within either a preset or an adjustable timeout period. write protection of cmos ram or eeprom. pulsed watchdog output to give advance warning of impending w d o assertion caused by watchdog timeout. applications computers critical ? power monitoring controllers intelligent instruments portable/battery- powered equipment features precision 4.65v voltage monitoring 200ms power-ok / reset time delay independent watchdog timer?reset or adjustable 1a standby current power switching 250ma output in v cc mode 25ma output in battery-backup mode on-board gating of chip-enable signals memory write-cycle completion 6ns ce gate propagation delay maxcap ? or supercap ? compatible voltage monitor for power-fail or low-battery warning backup-battery monitor guaranteed r e s e t valid to v cc = 1v ordering information 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 wdpo reset wdo ce in gnd v cc v out vbatt top view MAX791 ce out wdi lowline mr swt pfi pfo batt on dip/so/tssop cmos ram MAX791 reset lowline wdi ce in ce out +5v other system reset sources +12v v out vbatt * maxcap a0?15 mr +12v supply failure batt on swt address decode 0.1 f 0.1 f 0.47f* v cc pfi pfo gnd i/o p nmi int reset wdo pin configuration typical operating circuit part temp. range pin-package MAX791cpe 0? to +70? 16 plastic dip MAX791cse 0? to +70? 16 narrow so MAX791c/d 0? to +70? dice* MAX791epe -40? to +85? 16 plastic dip MAX791ese -40? to +85? 16 narrow so MAX791eje -40? to +85? 16 cerdip MAX791mje -55? to +125? 16 cerdip maxcap is a registered trademark of cesiwid inc. supercap is a registered trademark of baknor industries. * dice are specified at t a = +25?. for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. MAX791cue 0? to +70? 16 tssop MAX791eue -40? to +85? 16 tssop
MAX791 microprocessor supervisory circuit 2 _______________________________________________________________________________________ input voltage (with respect to gnd) v cc .......................................................................-0.3v to +6v vbatt..................................................................-0.3v to + 6v all other inputs.....................................-0.3v to (v out + 0.3v) input current v cc peak ..........................................................................1.0a v cc continuous ............................................................250ma vbatt peak ..................................................................250ma vbatt continuous ..........................................................25ma gnd, batt on .............................................................100ma all other outputs ............................................................25ma continuous power dissipation (t a = +70?) plastic dip (derate 10.53mw/? above +70?) ..........842mw narrow so (derate 8.70mw/? above +70?) ............696mw cerdip (derate 10.00mw/? above +70?) ...............800mw tssop (derate 6.70mw/? above +70?) ..................533mw operating temperature ranges MAX791c_ _ ......................................................o? to +70? MAX791e_ _ ....................................................-40? to +85? MAX791mje ..................................................-55? to +125? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v cc = 4.75v to 5.5v, vbatt = 2.8v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings parameter conditions supply current in battery-backup mode (excludes i out ) (note 2) min typ max units vbatt = 4.5v, i out = 20ma vbatt - 0.3 operating voltage range v cc , vbatt (note 1) 0 5.5 v v cc - 0.3 v cc - 0.2 v cc - 0.05 v cc - 0.02 vbatt-to-v out on-resistance 5 vbatt = 2.0v ? 17 30 ? battery-switchover threshold power down vbatt - 0.03 v v out in normal operating mode v cc = 3v, vbatt = 2.8v, i out = 100ma v cc - 0.2 v cc - 0.12 v v cc = 4.5v 0.8 1.6 0.8 1.2 v cc = 4.5v v cc - 0.40 vbatt = 2.8v, i out = 10ma vbatt - 0.25 0.04 1 supply current in normal operating mode (excludes i out ) v cc > vbatt - 1v 50 150 ? v cc -to-v out on-resistance v cc = 3v 1.2 2.0 ? vbatt = 4.5v 815 vbatt = 2.8v power up 13 25 vbatt + 0.03 v out in battery-backup mode vbatt = 2.0v, i out = 5ma vbatt - 0.15 v battery-switchover hysteresis 60 mv low-battery detector threshold 2 v i out = 250ma i out = 25ma MAX791c/e MAX791m MAX791c/e MAX791m v cc < vbatt - 1.2v, vbatt = 2.8v t a = +25? t a = t min to t max vbatt standby current (note 3) t a = t min to t max t a = +25? -1.0 0.02 ? vbatt + 0.2v v cc -0.1 0.02
ns MAX791 microprocessor supervisory circuit _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 4.75v to 5.5v, vbatt = 2.8v, t a = t min to t max , unless otherwise noted.) 0.7 1.5 i sink = 25ma ma 720 output source current w d p o output short-circuit current v 0.1 0.4 i sink = 3.2ma batt on output low voltage ms 10 4.7nf capacitor connected from swt to gnd minimum watchdog timeout period ms 1 w d p o pulse width ns 100 v il = 0.8v, v ih = 0.75 x v cc minimum watchdog input pulse width ? 80 power down v cc -to- l o w l i n e delay s 1.0 1.6 2.25 swt connected to v out v 4.50 4.65 4.75 r e s e t threshold voltage mv 150 l o w l i n e -to- r e s e t threshold voltage ? 100 power down v cc -to- r e s e t delay mv 15 r e s e t threshold hysteresis watchdog timeout period ns 70 w d p o -to- w d o delay ? ms 1 15 100 source current batt on output short-circuit current ma 60 sink current 140 200 280 power up units min typ max r e s e t active timeout period conditions parameter 0.004 0.3 MAX791e/m, i sink = 50?, v cc = 1.2v, v cc falling 0.1 0.4 i sink = 3.2ma, v cc = 4.25v v 3.5 i source = 1.6ma, v cc = 5v r e s e t output voltage ma 720 output source current r e s e t output short-circuit current 0.4 i sink = 3.2ma, v cc = 4.25v ? 15 100 output source current l o w l i n e output short-circuit current v 3.5 i source = 1?, v cc = 5v l o w l i n e output voltage 0.4 i sink = 3.2ma ma 310 output source current w d o output short-circuit current v 3.5 i source = 500?, v cc = 5v w d o output voltage 0.4 i sink = 3.2ma v 3.5 i source = 1ma w d p o output voltage 0.004 0.3 MAX791c, i sink = 50?, v cc = 1.0v, v cc falling reset, low-line, and watchdog timer
MAX791 microprocessor supervisory circuit 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = 4.75v to 5.5v, vbatt = 2.8v, t a = t min to t max , unless otherwise noted.) note 1: either v cc or vbatt can go to 0v, if the other is greater than 2.0v. note 2: the supply current drawn by the MAX791 from the battery (excluding i out ) typically goes to 10? when (vbatt - 1v) < v cc < vbatt. in most applications, this is a brief period as v cc falls through this region. note 3: "+" = battery-discharging current, "-" = battery-charging current. note 4: wdi is internally connected to a voltage-divider between v out and gnd. if unconnected, wdi is driven to 1.6v (typ), disabling the watchdog function. note 5: the chip-enable resistance is tested with v cc = 4.75v v c e in = v c e out = v cc / 2. note 6: the chip-enable propagation delay is measured from the 50% point at c e in to the 50% point at c e out. ns 610 50 ? source impedance driver, c load = 50pf c e in-to-c e out propagation delay (note 6) -50 -10 wdi = 0v ? 20 50 wdi = v out wdi input current 0.75 x v cc v ih ? 23 250 m r = 0v m r pull-up current ? 7 ? 75 150 enabled mode m r -to - r e s e t propagation delay c e in-to- c e out resistance (note 5) ? ?.005 ? disabled mode c e in leakage current ? 15 power down r e s e t -to- c e out delay na ?.01 ?5 pfi leakage current v 1.25 v cc = 5v m r threshold ma 0.1 0.75 2.0 ? disabled mode, c e out = 0v 25 15 c e out short-circuit current (reset active) v 1.20 1.25 1.30 v cc = 5v pfi input threshold v 0.8 v il wdi threshold voltage (note 4) units min typ max m r minimum pulse width conditions parameter 0.4 i sink = 3.2ma v 3.5 i source = 1?, v cc = 5v p f o output voltage ma 60 output sink current ? 1 15 100 output source current p f o short-circuit current ? 55 v in = 20mv, v od = 15mv pfi-to- p f o delay 15 v in = -20mv, v od = 15mv 3.5 v cc = 5v, i out = -100? v 2.7 v cc = 0v, vbatt = 2.8v, i out = 1? c e out output voltage high (reset active) power-fail comparator chip-enable gating manual reset input
MAX791 microprocessor supervisory circuit 58 38 -60 -30 30 150 v cc supply current vs. temperature (normal operating mode) 42 54 MAX791-01 temperature ( c) v cc supply current ( a) 0120 90 60 46 50 v cc = +5v vbatt = 2.8v pfi, ce in = 0v 4.80 4.30 4.40 4.35 -60 -30 30 150 reset threshold vs. temperature MAX791-07 temperature ( c) reset threshold (v) 0120 90 60 4.45 4.50 4.55 4.60 4.65 4.70 4.75 vbatt = 0v, power down 600 0 100 -60 -30 30 150 reset output resistance vs. temperature MAX791-08 temperature ( c) reset output resistance ( ? ) 0120 90 60 200 300 400 500 v cc = 0v, vbatt = 2.8v sinking current v cc = +5v, vbatt = 2.8v sourcing current 230 170 180 -60 -30 30 150 reset delay vs. temperature MAX791-09 temperature ( c) reset delay (ms) 0 120 90 60 190 200 210 220 v cc = 0v to 5v step vbatt = 2.8v typical operating characteristics (t a = +25?, unless otherwise noted.) 20 5 -60 -30 30 150 vbatt-to-v out on-resistance vs. temperature MAX791-04 temperature ( c) vbatt-to-v out on-resistance ( ? ) 0120 90 60 10 15 vbatt = 2.0v vbatt = 2.8v vbatt = 4.5v v cc = 0v 2.0 0 -60 -30 30 150 battery-supply current vs. temperature (battery-backup mode) 0.5 MAX791-02 temperature ( c) battery supply current ( a) 0120 90 60 1.0 1.5 v cc = 0v vbatt = 2.8v no load 120 40 -60 -30 30 150 180 chip-enable on-resistance vs. temperature 60 MAX791-03 temperature ( c) ce on-resistance ( ? ) 0120 90 60 80 100 v cc = +4.75v vbatt = 2.8v ce in = v cc /2 1.2 0.6 0.7 -60 -30 30 150 v cc -to-v out on-resistance vs. temperature MAX791-05 temperature (?) v cc -to-v out on-resistance ( ? ) 0 120 90 60 0.8 0.9 1.0 1.1 v cc = +5v, vbatt = 0v 1.50 0 0.25 -60 -30 30 150 pfi threshold vs. temperature MAX791-05 temperature ( c) pfi threshold (v) 0 120 90 60 0.50 0.75 1.00 1.25 v cc = +5v, vbatt = 0v, no load on pfo _______________________________________________________________________________________ 5
MAX791 microprocessor supervisory circuit 6 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) 1000 1 1 100 1000 v cc to v out vs. output current 10 100 MAX791-13 i out (ma) v cc - v out (mv) 10 v cc = 4.5v vbatt = 0v slope = 0.8 ? 1000 1 1 10 100 vbatt to v out vs. output current MAX791-14 i out (ma) vbatt - v out (mv) 10 100 v cc = 0v vbatt = 4.5v slope = 8 ? 0 50 0 40 20 watchdog timeout vs. timing capacitor MAX791-11 timing capacitor (nf) watchdog timeout (ms) 30 10 70 80 90 100 60 50 100 150 200 250 v cc = +5v vbatt = 2.8v 0 4 0 100 50 chip-enable propagation delay vs. ce out load capacitance MAX791-12 c load (pf) propagation delay (ns) 200 250 300 150 8 12 16 20 v cc = +5v ce in = 0v to 5v driver source impedance = 50 ? 0 4 8 15 battery current vs. input supply voltage MAX791-10 v cc (v) i batt ( a) 04 3 2 12 16 20 vbatt = 2.8v, i out = 0a
MAX791 microprocessor supervisory circuit _______________________________________________________________________________________ 7 pin description pin name function 1 vbatt 2v out output supply voltage. v out connects to v cc when v cc is greater than vbatt and v cc is above the reset threshold. when v cc falls below vbatt and v cc is below the reset threshold, v out connects to vbatt. connect a 0.1? capacitor from v out to gnd. 3v cc input supply voltage?5v input 4 gnd 5 batt on 6 p f o 7 pfi 8swt 9 m r 10 l o w l i n e 11 wdi 12 c e out chip-enable output. c e ? out goes low only when c e in is low and v cc is above the reset threshold. if c e in is low when reset is asserted, c e out will stay low for 15? or until c e in goes high, whichever occurs first. 13 c e in backup-battery input. connect to external battery or capacitor and charging circuit. ground. 0v reference for all signals. battery-on output. goes high when v out switches to vbatt. goes low when v out switches to v cc . connect the base of a pnp through a current-limiting resistor to batt on for v out current requirements greater than 250ma. power-fail output. this is the output of the power-fail comparator. p f o goes low when pfi is less than 1.25v. this is an uncommitted comparator, and has no effect on any other internal circuitry. power-fail input. this is the noninverting input to the power-fail comparator. when pfi is less than 1.25v, p f o goes low. connect pfi to gnd or v out when not used. set watchdog-timeout input. connect this input to v out to select the default 1.6s watchdog-timeout period. connect a capacitor between this input and gnd to select another watchdog-timeout period. watchdog-timeout period = 2.1 x (capacitor value in nf) ms. 16 w d p o 15 r e s e t 14 w d o manual-reset input. this input can be tied to an external momentary pushbutton switch, or to a logic gate out- put. r e s e t remains low as long as m r is held low and for 200ms after m r returns high. l o w l i n e output goes low when v cc falls to 150mv above the reset threshold. the output can be used to gen- erate an nmi if the unregulated supply is inaccessible. watchdog input. wdi is a three-level input. if wdi remains either high or low for longer than the watchdog time- out period, w d o goes low. w d o remains low until the next transition at wdi. leaving wdi unconnected disables the watchdog function. wdi connects to an internal voltage-divider between v out and gnd, which sets it to mid- supply when left unconnected. chip-enable input. the input to chip-enable gating circuit. connect to gnd or v out if not used. watchdog output. w d o goes low if wdi remains either high or low longer than the watchdog-timeout period. w d o returns high on the next transition at wdi. w d o remains high if wdi is unconnected. w d o is also high when r e s e t is asserted. r e s e t output goes low whenever v cc falls below the reset threshold. r e s e t will remain low for typically 200ms after v cc crosses the reset threshold on power-up. watchdog-pulse output. upon the absence of a tran sition at wdi, w d p o will pulse low for a minimum of 1ms. w d p o precedes w d o ? by 70ns.
_______________detailed description manual reset input many ?-based products require manual-reset capabil- ity, allowing the operator or test technician to initiate a reset. the manual reset input (mr) can be connected directly to a switch, without an external pull-up resistor or debouncing network. it connects to a 1.25v com- parator, and has a pull-up to v out as shown in figure 1. the propagation delay from asserting mr to reset asserted is 4? typ. pulsing mr low for a minimum of 15? resets all the internal counters, sets the watchdog output (wdo) and watchdog-pulse output (wdpo) high, and sets the set watchdog-timeout (swt) input to v out - 0.6v, if it is not already connected to v out (for internal timeouts). it also disables the chip-enable function, setting the chip-enable output (ce out) to a high state. the reset output remains active as long as mr is held low, and the reset-timeout period begins after mr returns high (figure 2). use this input as either a digital-logic input or a second low-line comparator. normal ttl/cmos levels can be wire-or connected via pull-down diodes (figure 3), and open-drain/collector outputs can be wire-ored directly. MAX791 microprocessor supervisory circuit 8 _______________________________________________________________________________________ MAX791 chip-enable output control v cc 3 1 13 9 8 11 7 vbatt ce in mr swt wdi pfi reset generation timebase for reset and watchdog watchdog transition detector watchdog timer v out 1.25v gnd 4 4.65v 150mv 10 lowline 5 2 12 15 16 14 pfo wdo wdpo reset ce out 6 v out batt on figure 1. MAX791 block diagram mr reset ce in 0v 7.5 s typ 15 s typ 25 s min ce out figure 2. manual-reset timing diagram MAX791 * * other reset sources manual reset mr * diodes not required on open-drain outputs figure 3. diode "or" connections allow multiple reset sources to connect to mr
reset output the MAX791? reset output ensures that the ? pow- ers up in a known state, and prevents code-execution errors during power-down or brownout conditions. the reset output is active low, and typically sinks 3.2ma at 0.1v saturation voltage in its active state. when deasserted, reset sources 1.6ma at typically v out - 0.5v. when no backup battery is used, reset output is guaranteed to be valid down to v cc = 1v, and an external 10k ? pull-down resistor on reset ensures that reset will be valid with v cc down to gnd (figure 4). as v cc goes below 1v, the gate drive to the reset output switch reduces accordingly, increasing the r ds(on) and the saturation voltage. the 10k ? pull-down resistor ensures the parallel combination of switch plus resistor is around 10k ? and the output saturation volt- age is below 0.4v while sinking 40?. when using a 10k ? external pull-down resistor, the high state for the reset output with v cc = 4.75v is 4.5v typ. for battery voltages 2v connected to vbatt, reset remains valid for v cc from 0v to 5.5v. reset will be asserted during the following conditions: ? cc < 4.65v (typ). mr < 1.25v (typ). reset remains asserted for 200ms (typ) after v cc rises above 4.65v or after mr has exceeded 1.25v. the MAX791 battery-switchover comparator does not affect reset assertion. however, reset is asserted in battery-backup mode since v cc must be below the reset threshold to enter this mode. watchdog function the watchdog monitors ? activity via the watchdog input (wdi). if the ? becomes inactive, wdo and wdpo are asserted. to use the watchdog function, connect wdi to a bus line or ? i/o line. if wdi remains high or low for longer than the watchdog timeout period (1.6s nominal), wdpo and wdo are asserted, indicat- ing a software fault condition (see watchdog output and watchdog-pulse output sections). watchdog input a change of state (high to low, low to high, or a mini- mum 100ns pulse) at wdi during the watchdog period resets the watchdog timer. the watchdog default time- out is 1.6s. select alternative timeout periods by con- necting an external capacitor from swt to gnd (see selecting an alternative watchdog timeout period sec- tion). to disable the watchdog function, leave wdi floating. an internal resistor network (100k ? equivalent imped- ance at wdi) biases wdi to approximately 1.6v. internal comparators detect this level and disable the watchdog timer. when v cc is below the reset thresh- old, the watchdog function is disabled and wdi is dis- connected from its internal resistor network, thus becoming high impedance. watchdog output wdo remains high if there is a transition or pulse at wdi during the watchdog-timeout period. the watch- dog function is disabled and wdo is a logic high when v cc is below the reset threshold, battery-backup mode is enabled, or wdi is an open circuit. in watchdog mode, if no transition occurs at wdi during the watch- dog-timeout period, wdo goes low 70ns after the falling edge of wdpo and remains low until the next transition at wdi (figure 5). a flip-flop can force the system into a hardware shutdown if there are two suc- cessive watchdog faults (figure 6). wdo has a 2 x ttl output characteristic. MAX791 microprocessor supervisory circuit _______________________________________________________________________________________ 9 MAX791 reset 10k to p reset 15 figure 4. adding an external pull-down resistor ensures r e s e t is valid with v cc down to gnd wdpo wdi 70ns 1.6s 100ns min wdo figure 5. wdi, w d o , and w d p o timing diagram (v cc mode)
MAX791 watchdog-pulse output as described in the preceding section, wdpo can be used as the clock input to an external d flip-flop. upon the absence of a watchdog edge or pulse at wdi at the end of a watchdog-timeout period, wdpo will pulse low for 1ms. the falling edge of wdpo precedes wdo by 70ns. since wdo is high when wdpo goes low, the flip-flop? q output remains high as wdo goes low (figure 5). if the watchdog timer is not reset by a transi- tion at wdi, wdo remains low and wdpo clocks a logic low to the q output, causing the MAX791 to latch in reset. if the watchdog timer is reset by a transition at wdi, wdo goes high and the flip-flop? q output remains high. thus, a system shutdown is only caused by two successive watchdog faults. the internal pull-up resistors associated with wdo and wdpo connect to v out . therefore, do not connect these outputs directly to cmos logic that is powered from v cc since, in the absence of v cc (i.e., battery mode), excessive current will flow from wdo or wdpo through the protection diode(s) of the cmos- logic inputs to ground. selecting an alternative watchdog- timeout period swt input controls the watchdog-timeout period. connecting swt to v out selects the internal 1.6s watch- dog-timeout period. select an alternative timeout period by connecting a capacitor between swt and gnd. do not leave swt floating, and do not connect it to ground. the following formula determines the watchdog-timeout period: watchdog-timeout period = 2.1 x (capacitor value in nf) ms this formula is valid for capacitance values between 4.7nf and 100nf (see the watchdog timeout vs. timing capacitor graph in the typical operating characteristics ). swt is internally connected to a ?00na (typ) current source, which charges and dis- charges the timing capacitor to create the oscillator fre- quency that sets the watchdog-timeout period (see connecting a timing capacitor to swt section). chip-enable signal gating the MAX791 provides internal gating of chip-enable (ce) signals to prevent erroneous data from corrupting the cmos ram in the event of a power failure. during normal operation, the ce gate is enabled and passes all ce transitions. when reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the cmos ram. the MAX791 uses a series transmission gate from the chip-enable input (ce in) to ce out (figure 1). the 10ns max ce propagation from ce in to ce out microprocessor supervisory circuit 10 ______________________________________________________________________________________ MAX791 clock v cc cd4013 v cc gnd v out mr 0.1 f 4.7k *sets q high on power-up vbatt reset wdi wdpo wdo p power p reset two consecutive watchdog fault indications i/o q d q set reset v ss 2 15 11 lowline nmi interrupt 10 16 1/6 74hc04 14 1 5 3 14 3 2 7 4 6 *1 f +5v 1 9 4 reactivate +5v 3.6v figure 6. two consecutive watchdog faults latch the system in reset
enables the MAX791 to be used with most ?s. chip-enable input ce in is high impedance (disabled mode) while reset is asserted. during a power-down sequence where v cc passes 4.65v, ce in assumes a high-impedance state when the voltage at ce in goes high or 15? after reset is asserted, whichever occurs first (figure 7). during a power-up sequence, ce in remains high impedance, regardless of ce in activity, until reset is deasserted following the reset-timeout period. in the high-impedance mode, the leakage currents into this input are ?? max over temperature. in the low- impedance mode, the impedance of ce in appears as a 75 ? resistor in series with the load at ce out. the propagation delay through the ce transmission gate depends on both the source impedance of the drive to ce in and the capacitive loading on ce out (see the chip-enable propagation delay vs. ce out load capacitance graph in the typical operating characteristics ). the ce propagation delay is produc- tion tested from the 50% point on ce in to the 50% point on ce out using a 50 ? driver and 50pf of load capacitance (figure 8). for minimum propagation delay, minimize the capacitive load at ce out and use a low output-impedance driver. chip-enable output in the enabled mode, the impedance of ce out is equivalent to 75 ? in series with the source driving ce in. in the disabled mode, the 75 ? transmission gate is off and ce out is actively pulled to v out . this source turns off when the transmission gate is enabled. lowline output the low-line comparator monitors v cc with a typical threshold voltage 150mv above the reset threshold, and has 15mv of hysteresis. lowline typically sinks 3.2ma at 0.1v. for normal operation (v cc above the lowline threshold), lowline is pulled to v out . if access to the unregulated supply is unavailable, use lowline to provide a nonmaskable interrupt (nmi) to the ? as v cc begins to fall (figure 9a). power-fail comparator the power-fail comparator is an uncommitted compara- tor that has no effect on the other functions of the ic. common uses include monitoring supplies other than 5v (see the typical operating circuit and the monitoring a negative voltage section) and early power-fail detection when the unregulated power is easily accessible (figure 9b). MAX791 microprocessor supervisory circuit ______________________________________________________________________________________ 11 v cc ce in reset threshold ce out reset reset 100 s 15 s 100 s figure 7. reset and chip-enable timing MAX791 ce in c load ce out gnd +5v 50 ? driver v cc figure 8. ce propagation delay test circuit
MAX791 power-fail input pfi is the input to the power-fail comparator. pfi has a guaranteed input leakage of ?5na max over tempera- ture. the typical comparator delay is 15? from v il to v ol (power failing), and 55? from v ih to v oh (power being restored). if unused, connect this input to ground. power-fail output the power-fail output (pfo) goes low when pfi goes below 1.25v. it typically sinks 3.2ma with a saturation voltage of 0.1v. with pfi above 1.25v, pfo is actively pulled to v out . connecting pfi through a voltage- divider to an unregulated supply allows pfo to gener- ate an nmi as the unregulated power begins to fall (figure 9b). if the unregulated supply is inaccessible, use lowline to generate the nmi. the lowline threshold is typically 150mv above the reset threshold (see lowline output section). battery-backup mode the MAX791 requires two conditions to switch to bat- tery-backup mode: 1) v cc must be below the reset threshold; 2) v cc must be below vbatt. table 1 lists the status of the inputs and outputs in battery-backup mode. microprocessor supervisory circuit 12 ______________________________________________________________________________________ table 1. input and output states in battery-backup mode * v cc must be below the reset threshold to enter battery- backup mode. logic high. the open-circuit output voltage is equal to v out . w d p o 16 logic low* r e s e t 15 logic high. the open-circuit output voltage is equal to v out . w d o 14 high impedance c e in 13 logic high. the open-circuit output voltage is equal to v out . c e out 12 wdi is ignored, and goes high impedance. wdi 11 logic low* l o w l i n e 10 m r ? is ignored. m r 9 swt is ignored. swt 8 the power-fail comparator remains active in the battery-backup mode for v cc vbatt - 1.2v typ. pfi 7 the power-fail comparator remains active in the battery-backup mode for v cc vbatt - 1.2v typ. below this voltage, p f o is forced low. p f o 6 logic high. the open-circuit output is equal to v out . batt on 5 gnd?v reference for all signals. gnd 4 battery-switchover comparator monitors v cc for active switchover. v cc 3 v out is connected to vbatt through an internal pmos switch. v out 2 supply current is 1? maximum. vbatt 1 status name pin MAX791 v out v cc from regulated supply power to cmos ram vbatt reset lowline wdi gnd reset nmi i/o line p p power 2 0.1 f 0.1 f 3.0v 1 3 4 a) b) 15 10 11 MAX791 v out v cc pfi power to cmos ram vbatt reset pfo wdi gnd voltage regulator reset nmi i/o line p p power 2 0.1 f 0.1 f 3.0v 1 3 7 4 15 6 11 figure 9. a) if the unregulated supply is inaccessible, lowline generates the nmi for the ?. b) use pfo to gener- ate the ? nmi if the unregulated supply is inaccessible.
battery on output the battery on (batt on) output indicates the status of the internal v cc /battery-switchover comparator, which controls the internal v cc and vbatt switches. for v cc greater than vbatt (ignoring the small hys- teresis effect), batt on typically sinks 3.2ma at 0.1v saturation voltage. in battery-backup mode, this termi- nal sources approximately 10? from v out . use batt on to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-cur- rent applications (see typical operating circuit ). input supply voltage the input supply voltage (v cc ) should be a regulated +5v. v cc connects to v out via a parallel diode and a large pmos switch. the switch carries the entire cur- rent load for currents less than 250ma. the parallel diode carries any current in excess of 250ma. both the switch and the diode have impedances less than 1 ? each (figure 10). the maximum continuous current is 250ma, but power-on transients may reach a maximum of 1a. backup-battery input the backup-battery input (vbatt) is similar to v cc , except the pmos switch and parallel diode are much smaller. accordingly, the on-resistances of the diode and the switch are each approximately 10 ? . continuous current should be limited to 25ma and peak currents (only during power-up) limited to 250ma. the reverse leakage of this input is less than 1? over tem- perature and supply voltage. output supply voltage the output supply voltage (v out ) is internally connect- ed to the substrate of the ic and supplies all the current to the external system and internal circuitry. all open- circuit outputs will, for example, assume the v out volt- age in their high states rather than the v cc voltage. at the maximum source current of 250ma, v out will typi- cally be 200mv below v cc . decouple this terminal with a 0.1? capacitor. low-battery monitor the MAX791 low-battery voltage function monitors vbatt. low-battery detection of 2.0v ?.15v is moni- tored only during the reset-timeout period (200ms) that occurs either after a normal power-up sequence or after the mr reset input has been returned to its high state. if the battery voltage is below 2.0v, the second ce pulse is inhibited after reset timeout. if the battery voltage is above 2.0v, all ce pulses are allowed through the ce gate after the reset timeout period. to use this function, after the 200ms reset delay, write 00 (hex) to a location using the first ce pulse, and write ff (hex) to the same location using the second ce pulse following reset going inactive on power-up. the contents of the memory then indicates a good battery (ff) or a low battery (00) (figure 11). MAX791 microprocessor supervisory circuit ______________________________________________________________________________________ 13 200ms typ reset threshold v cc reset ce in ce out second ce pulse absent when vbatt < 2v figure 11. backup-battery monitor timing diagram MAX791 vbatt v cc 1 3 2 0.1 f v out figure 10. v cc and vbatt-to-v out switch
MAX791 applications information the MAX791 is not short-circuit protected. shorting v out to ground, other than power-up transients such as charging a decoupling capacitor, destroys the device. all open-circuit outputs swing between v out and gnd rather than v cc and gnd. if long leads connect to the chip inputs, ensure that these lines are free from ringing and other conditions that would forward bias the chip? protection diodes. there are three distinct modes of operation: 1) normal operating mode with all circuitry powered up. typical supply current from v cc is 60?, while only leakage currents flow from the battery. 2) battery-backup mode where v cc is typically within 0.7v below vbatt. all circuitry is powered up and the supply current from the battery is typically less than 60?. 3) battery-backup mode where v cc is less than vbatt by at least 0.7v. vbatt supply current is less than 1? max. using supercaps or maxcaps with the MAX791 vbatt has the same operating voltage range as v cc , and the battery-switchover threshold voltages are typi- cally ?0mv centered at vbatt, allowing use of a supercap and a simple charging circuit as a backup source (figure 12). if v cc is above the reset threshold and vbatt is 0.5v above v cc , current flows to v out and v cc from vbatt until the voltage at vbatt is less than 0.5v above v cc . for example, with a supercap connected to vbatt and through a diode to v cc , if v cc quickly changes from 5.4v to 4.9v, the capacitor discharges through v out and v cc until vbatt reaches 5.3v typ. leakage current through the supercap charging diode and MAX791 internal power diode eventually discharges the supercap to v cc . also, if v cc and vbatt start from 0.5v above the reset threshold and power is lost at v cc , the supercap on vbatt discharges through v cc until vbatt reaches the reset threshold; the MAX791 then switches to battery-backup mode and the current through v cc goes to zero (figure 10). using separate power supplies for vbatt and v cc if using separate power supplies for v cc and vbatt, vbatt must be less than 0.3v above v cc when v cc is above the reset threshold. as described in the previous section, if vbatt exceeds this limit and power is lost at v cc , current flows continuously from vbatt to v cc via the vbatt-to-v out diode and the v out -to-v cc switch until the circuit is broken (figure 10). alternative chip-enable gating using memory devices with ce and ce inputs allows the MAX791 ce loop to be bypassed. to do this, con- nect ce in to ground, pull up ce out to v out , and connect ce out to the ce input of each memory device (figure 13). the ce input of each part then con- nects directly to the chip-select logic, which does not have to be gated by the MAX791. adding hysteresis to the power-fail comparator hysteresis adds a noise margin to the power-fail com- parator and prevents repeated triggering of pfo when vin is near the power-fail comparator trip point. figure 14 shows how to add hysteresis to the power-fail com- parator. select the ratio of r1 and r2 so that pfi sees 1.25v when vin falls to the desired trip point (v trip ). resistor r3 adds hysteresis. it will typically be an order of magnitude greater than r1 or r2. the current through r1 and r2 should be at least 1? to ensure that the 25na (max) pfi input current does not shift the trip point. r3 should be larger than 10k ? to prevent it from loading down the pfo pin. capacitor c1 adds additional noise rejection. microprocessor supervisory circuit 14 ______________________________________________________________________________________ MAX791 1 0.47f 1n4148 +5v 2 3 v cc gnd vbatt 4 v out figure 12. supercap or maxcap on vbatt
monitoring a negative voltage the power-fail comparator can be used to monitor a negative supply voltage using figure 15? circuit. when the negative supply is valid, pfo is low. when the neg- ative supply voltage drops, pfo goes high. this cir- cuit? accuracy is affected by the pfi threshold toler- ance, the v cc voltage, and resistors r1 and r2. backup-battery replacement the backup battery may be disconnected while v cc is above the reset threshold. no precautions are neces- sary to avoid spurious reset pulses. negative-going v cc transients while issuing resets to the ? during power-up, power- down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going v cc transients (glitches). it is usually undesirable to reset the ? when v cc experiences only small glitches. figure 16 shows maximum transient duration vs. reset comparator overdrive, for which reset pulses are not generated. the graph was produced using negative- going v cc pulses, starting at 5v and ending below the reset threshold by the magnitude indicated (reset com- parator overdrive). the graph shows the maximum pulse width that a negative-going v cc transient may typically have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. typically, a v cc tran- sient that goes 100mv below the reset threshold and lasts for 40? or less will not cause a reset pulse to be issued. a 100nf bypass capacitor mounted close to the v cc pin provides additional transient immunity. connecting a timing capacitor to swt swt is internally connected to a ?00na current source. when a capacitor is connected from swt to ground (to select an alternative watchdog-timeout peri- od), the current source charges and discharges the timing capacitor to create the oscillator that controls the watchdog-timeout period. to prevent timing errors or oscillator start-up problems, minimize external current leakage sources at this pin, and locate the capacitor as MAX791 microprocessor supervisory circuit ______________________________________________________________________________________ 15 MAX791 v cc gnd pfi *optional r2 r3 r1 v in +5v c1* to p pfo v trip = 1.25 r1 + r2 r2 v h = 1.25 / r2 || r3 vl - 1.25 + 5 - 1.25 = 1.25 r1 + r2 || r3 r1 r3 r2 pfo +5v 0v 0v v h v trip v in v l figure 14. adding hysteresis to the power-fail comparator MAX791 v out gnd ce in ce ce ce out ce ce ce ce ce ce *maximum rp value depends on the number of rams. minimum rp value is 1k ? active-high ce lines from logic ram 1 ram 2 ram 3 ram 4 rp* figure 13. alternate ce gating
MAX791 close to swt as possible. the sum of pc board leak- age + swt capacitor leakage must be small compared to ?00na. watchdog software considerations a way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than ?ulsing?the watchdog input high-low-high or low-high-low. this technique avoids a ?tuck?loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. figure 17 shows an example flow diagram where the i/o driving the watchdog input is set high at the begin- ning of the program, set low at the beginning of every subroutine or loop, then set high again when the pro- gram returns to the beginning. if the program should ?ang?in any subroutine, the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. maximum v cc fall time the v cc fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03v/?. a standard rule of thumb for filter capacitance on most regulators is on the order of 100? per amp of current. when the power supply is shut off or the main battery is disconnected, the associ- ated initial v cc fall rate is just the inverse or 1a / 100? = 0.01v/?. the v cc fall rate decreases with time as v cc falls exponentially, which more than satisfies the maximum fall-time requirement. microprocessor supervisory circuit 16 ______________________________________________________________________________________ 100 0 10 1000 10,000 40 20 80 60 MAX791-16 reset comparator overdrive (mv) (reset threshold voltage - v cc ) maximum transient duration ( s) 100 v cc = +5v t a = +25 c 0.1 f capacitor from v out to gnd figure 16. maximum transient duration without causing a reset pulse vs. reset comparator overdrive MAX791 v cc gnd pfi r2 r1 +5v pfo pfo +5v 0v note : v trip is negative 0v v trip v- 5 - 1.25 = 1.25 - v trip r1 r2 v- figure 15. monitoring a negative voltage
MAX791 microprocessor supervisory circuit ______________________________________________________________________________________ 17 start set wdi low subroutine or program loop, set wdi high return end figure 17. watchdog flow diagram reset gnd v cc pfo batt on v out vbatt swt pfi 0.11" (2.794mm) 0.07" (1.778mm) wdpo wdo ce in ce out mr lowline wdi chip topography transistor count: 729 substrate connected to v out
MAX791 microprocessor supervisory circuit 18 ______________________________________________________________________________________ ________________________________________________________package information dim a a1 a2 a3 b b1 c d1 e e1 e ea eb l min 0.015 0.125 0.055 0.016 0.045 0.008 0.005 0.300 0.240 0.100 0.300 0.115 max 0.200 0.175 0.080 0.022 0.065 0.012 0.080 0.325 0.310 0.400 0.150 min 0.38 3.18 1.40 0.41 1.14 0.20 0.13 7.62 6.10 2.54 7.62 2.92 max 5.08 4.45 2.03 0.56 1.65 0.30 2.03 8.26 7.87 10.16 3.81 inches millimeters plastic dip plastic dual-in-line package (0.300 in.) dim d d d d d d min 0.348 0.735 0.745 0.885 1.015 1.14 max 0.390 0.765 0.765 0.915 1.045 1.265 min 8.84 18.67 18.92 22.48 25.78 28.96 max 9.91 19.43 19.43 23.24 26.54 32.13 inches millimeters pins 8 14 16 18 20 24 c a a2 e1 d e ea eb a3 b1 b 0 - 15 a1 l d1 e dim a a1 b c e e h l min 0.053 0.004 0.014 0.007 0.150 0.228 0.016 max 0.069 0.010 0.019 0.010 0.157 0.244 0.050 min 1.35 0.10 0.35 0.19 3.80 5.80 0.40 max 1.75 0.25 0.49 0.25 4.00 6.20 1.27 inches millimeters 21-0041a so small outline package (0.150 in.) dim d d d min 0.189 0.337 0.386 max 0.197 0.344 0.394 min 4.80 8.55 9.80 max 5.00 8.75 10.00 inches millimeters pins 8 14 16 1.27 0.050 l 0 -8 h e d e a a1 c 0.101mm 0.004in. b
MAX791 microprocessor supervisory circuit ______________________________________________________________________________________ 19 c 0 -15 a d b1 b dim a b b1 c e e1 e l l1 q s s1 min 0.014 0.038 0.008 0.220 0.290 0.125 0.150 0.015 0.005 max 0.200 0.023 0.065 0.015 0.310 0.320 0.200 0.070 0.098 min 0.36 0.97 0.20 5.59 7.37 3.18 3.81 0.38 0.13 max 5.08 0.58 1.65 0.38 7.87 8.13 5.08 1.78 2.49 2.54 0.100 q l s1 e cerdip ceramic dual-in-line package (0.300 in.) s l1 e e1 pins 8 14 16 18 20 24 dim d d d d d d min max 0.405 0.785 0.840 0.960 1.060 1.280 min max 10.29 19.94 21.34 24.38 26.92 32.51 inches milli meters inches millimeters package information (continued) tssop.eps
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 ? 2000 maxim integrated products printed usa is a registered trademark of maxim integrated products. MAX791 microprocessor supervisory circuit notes

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